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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11039-4E
MEMORY
CMOS
2 x 512 K x 16 BIT SYNCHRONOUS DYNAMIC RAM
MB81F161622B-60/-70/-80
CMOS 2-Bank x 524,288-Word x 16 Bit Synchronous Dynamic Random Access Memory s DESCRIPTION
The Fujitsu MB81F161622B is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing 16,777,216 memory cells accessible in an 16-bit format. The MB81F161622B features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81F161622B SDRAM is designed to reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a standard DRAM. The MB81F161622B is ideally suited for laser printers, high resolution graphic adapters, accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed.
s PRODUCT LINE & FEATURES
MB81F161622B Parameter
CL - tRCD - tRP
-60 3 - 3 - 3 clk min. 167 MHz max. 6.0 ns min. 5.5 ns max. 200 mA max. 400A max. 400A max.
-70 3 - 3 - 3 clk min. 143 MHz max. 7.0 ns min. 6 ns max. 180 mA max. 400A max. 400A max.
-80 3 - 3 - 3 clk min. 125 MHz max. 8.0 ns min. 6 ns max. 160 mA max. 400A max. 400A max.
Reference Spec (100MHz @CL=3) 3 - 3 - 3 clk min. 100 MHz max. 10 ns min. 6 ns max. 140 mA max. 400A max. 400A max.
Clock Frequency (CL = 3) Burst Mode Cycle Time (CL = 3) Access Time From Clock (CL = 3) Operating Current (Two Banks Active) Power Down Mode Current (ICC2P) Self Refresh Mode Current (ICC6)
* Single +3.3 V Supply: +0.3 V / -0.15 V tolerance (-60) 0.3 V tolerance (-70/-80) * LVTTL compatible I/O interface * 4 K refresh cycles every 64 ms * Dual banks operation * Burst read/write operation and burst read/single write operation capability * Byte control by DQMU/DQML
* Programmable burst type, burst length, and CAS latency * Auto-and Self-refresh (every 15.6 s) * CKE power down mode * Output Enable and Input Data Mask * 167 MHz/143MHz/125 MHz clock frequency
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MB81F161622B-60/-70/-80
s PACKAGE
50-pin plastic TSOP (II)
Marking side
(FPT-50P-M05) (Normal Bend)
Package and Ordering Information
- 50-pin plastic (400 mil) TSOP-II with normal bend leads,order as MB81F161622B-xxFN
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MB81F161622B-60/-70/-80
s PIN ASSIGNMENTS AND DESCRIPTIONS
50-Pin TSOP (II) (TOP VIEW)
VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ DQML WE CAS RAS CS A11 A10/AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VCCQ DQ11 DQ10 VSSQ DQ9 DQ8 VCCQ DU DQMU CLK CKE DU A9 A8 A7 A6 A5 A4 VSS
(Marking side)
Pin Number 1, 7, 13, 25, 38, 44 2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42, 43, 45, 46, 48, 49 4, 10, 26, 41, 47, 50 37 15 16 17 18 19 20 20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32 33 34 35 14, 36
Symbol VCC, VCCQ DQ0 to DQ15 VSS, VSSQ* DU WE CAS RAS CS A11 (BA) AP A0 to A10 DU CKE CLK DQML, DQMU
Description Supply Voltage Data I/O Ground Don't use (leave open) Write Enable Column Address Strobe Row Address Strobe Chip Select Bank Select Auto Precharge Enable Address Input * Row: A0 to A10 * Column: A0 to A7
Don't use (leave open) Clock Enable Clock Input Input Mask/Output Enable
* : These pins are connected internally in the chip.
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MB81F161622B-60/-70/-80
s BLOCK DIAGRAM
Fig. 1 - MB81F161622B BLOCK DIAGRAM
CLK CLOCK BUFFER CKE
To each block
BANK-1
BANK-0 RAS CS CONTROL SIGNAL LATCH COMMAND DECODER WE
CAS
RAS CAS WE
MODE REGISTER
DRAM CORE (2,048 x 256 x 16)
A0 to A11, AP
ADDRESS BUFFER/ REGISTER
ROW ADDR.
DQML DQMU
I/O DATA BUFFER/ REGISTER
COLUMN ADDRESS COUNTER DQMU
COL. ADDR. I/O
VCC VCCQ VSS/VSSQ
DQ0 to DQ15
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MB81F161622B-60/-70/-80
s FUNCTIONAL TRUTHAL TABLE (Note 1)
COMMAND TRUTH TABLE Notes 2,3,4
Function Device Deselect No Operation Burst Stop Read Read with Auto-precharge Write Write with Auto-precharge Bank Active (RAS) Precharge Single Bank Precharge All Banks Mode Register Set Notes: *1. *2. *3. *4. *5. *6. *8,9 *6 *6 *7 Notes Symbol *5 *5 DESL NOP BST READ WRIT ACTV PRE PALL MRS *6 READA *6 WRITA CKE n-1 H H H H H H H H H H H n X X X X X X X X X X X CS H L L L L L L L L L L A11 A10 RAS CAS WE (BA) (AP) A9, A8 X H H H H H H L L L L X H H L L L L H H H L X H L H H L L H L L L X X X V V V V V V X L X X X L H L H V L H L X X X X X X X V X X V A7 to A0 X X X V V V V V X X V
V = Valid, L = Logic Low, H = Logic High, X = either L or H All commands assume no CSUS command on previous rising edge of clock. All commands are assumed to be valid state transitions. All inputs are latched on the rising edge of clock. NOP and DESL commands have the same effect on the part. READ, READA, WRIT, and WRITA commands should only be issued after the corresponding bank has been activated (ACTV command). Refer to STATE DIAGRAM. *7. ACTV command should only be asserted after corresponding bank has been precharged (PRE or PALL command). *8. Required after power up. *9. MRS command should only be issued after all banks have been precharged (PRE or PALL command). Refer to STATE DIAGRAM.
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MB81F161622B-60/-70/-80
DQM TRUTH TABLE
Function Data Write/Output Enable for Lower Byte Data Write/Output Enable for Upper Byte Data Mask/Output Disable for Lower Byte Data Mask/Output Disable for Upper Byte Command ENBL L ENBL U MASK L MASK U CKE n-1 H H H H n X X X X DQML L X H X DQMU X L X H
CKE TRUTH TABLE
Current State Function Notes Symbol CSUS CKE n-1 H L L *2 *2,*3 REF SELF SELFX *3 PD H H L L H H L L n L L H H L H H L L H H CS X X X L L L H L H L H RAS CAS WE X X X L L H X H X H X X X X L L H X H X H X X X X H H H X H X H X A11 A10 A9 to (BA) (AP) A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Bank Active Clock Suspend Mode Entry*1,*4 Any Except to Idle Clock Suspend Idle Idle Self-refresh Idle Clock Suspend Continue Clock Suspend Mode Exit Auto-refresh Command Self-refresh Entry Self-refresh Exit Power Down Entry *1
Power Down Power Down Exit
Notes: *1. The CSUS command requires that at least one bank is active. Refer to STATE DIAGRAM. *2. REF and SELF commands should only be issued after all banks have been precharged (PRE or PAL command). Refer to STATE DIAGRAM. *3. Self and PD commands should only be issued after the last data have been appeared on DQ. *4. NOP or DSEL commands should only be issued after CSUS and PRE(or PALL) commands asserted at same time.
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MB81F161622B-60/-70/-80
OPERATION COMMAND TABLE (Applicable to single bank)
Current State Idle CS H L L L L L L L L Bank Active H L L L L L L L L RAS CAS WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Addr X X X Command DESL NOP BST NOP NOP NOP *2 *2 Function Notes
BA, CA, AP READ/READA Illegal BA, CA, AP BA, RA BA, AP X MODE X X X WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF MRS DESL NOP BST Bank Active after tRCD NOP Auto-refresh or Self-refresh Mode Register Set (Idle after tRSC) NOP NOP NOP
*6 *3 *3,*7
BA, CA, AP READ/READA Begin Read; Determine AP BA, CA, AP BA, RA BA, AP X MODE WRIT/WRITA Begin Write; Determine AP ACTV PRE/PALL REF/SELF MRS Illegal Precharge; Determine Precharge Type Illegal Illegal *2
(Continued)
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MB81F161622B-60/-70/-80
Current State Read
CS
RAS CAS WE
Addr
Command
Function NOP (Continue Burst to End Bank Active) NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, New Read; Determine AP Terminate Burst, Start Write; Determine AP Illegal Terminate Burst, Precharge; Idle Determine Precharge Type Illegal Illegal NOP (Continue Burst to End Bank Active) NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, Start Read; Determine AP Terminate Burst, New Write; Determine AP Illegal Terminate Burst, Precharge; Determine Precharge Type Illegal Illegal
Notes
H
X
X
X
X
DESL
L L L
H H H
H H L
H L H
X X
NOP BST
BA, CA, AP READ/READA
L L L L L Write H
H L L L L X
L H H L L X
L H L H L X
BA, CA, AP BA, RA BA, AP X MODE X
WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL
*4 *2
L L L
H H H
H H L
H L H
X X
NOP BST
BA, CA, AP READ/READA
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, AP BA, RA BA, AP X MODE
WRIT/WRITA ACTV PRE/PALL REF/SELF MRS
*2
(Continued)
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MB81F161622B-60/-70/-80
Current State Read with Autoprecharge
CS
RAS CAS WE
Addr
Command
Function NOP (Continue Burst to End Precharge Idle) NOP (Continue Burst to End Precharge Idle) Illegal
Notes
H
X
X
X
X
DESL
L L L L L L L L Write with Autoprecharge H
H H H H L L L L X
H H L L H H L L X
H L H L H L H L X
X X
NOP BST
BA, CA, AP READ/READA Illegal BA, CA, AP BA, RA BA, AP X MODE X WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF MRS DESL Illegal Illegal Illegal Illegal NOP (Continue Burst to End Precharge Idle) NOP (Continue Burst to End Precharge Idle) Illegal
*2 *2 *2 *2
L L L L L L L L
H H H H L L L L
H H L L H H L L
H L H L H L H L
X X
NOP BST
BA, CA, AP READ/READA Illegal BA, CA, AP BA, RA BA, AP X MODE WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF MRS Illegal Illegal Illegal Illegal
*2 *2 *2 *2
(Continued)
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MB81F161622B-60/-70/-80
Current State Precharge
CS H L L L L L L L L
RAS CAS WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L
Addr X X X
Command DESL NOP BST
Function NOP (Idle after tRP) NOP (Idle after tRP) Illegal
Notes
BA, CA, AP READ/READA Illegal BA, CA, AP BA, RA BA, AP X MODE X X X WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF MRS DESL NOP BST Illegal NOP (PALL may effect other bank) Illegal Illegal NOP (Bank Active after tRCD) NOP (Bank Active after tRCD) NOP (Bank Active after tRCD)
*2 *2 *2 *5
Bank Activating
H L L L L L L L L
BA, CA, AP READ/READA Illegal BA, CA, AP BA, RA BA, AP X MODE WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF MRS Illegal Illegal Illegal Illegal
*2 *2 *2 *2
(Continued)
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MB81F161622B-60/-70/-80
(Continued)
Current State Refreshing CS H L L RAS CAS WE X H H X H L X X X Addr X X X Command DESL NOP/BST Function NOP (Idle after tRC) NOP (Idle after tRC) Notes
READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL REF/SELF/ MRS DESL NOP BST Illegal
L
L
H
X
X
L Mode Register Setting H L L L
L X H H H
L X H H L
X X H L X
X X X X X
Illegal NOP (Idle after tRSC) NOP (Idle after tRSC) Illegal
READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL/REF/ SELF/MRS
L
L
X
X
X
Illegal
ABBREVIATIONS: RA = Row Address CA = Column Address
BA = Bank Address AP = Auto Precharge
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MB81F161622B-60/-70/-80
COMMAND TRUTH TABLE FOR CKE
Current State Selfrefresh CKE CKE n-1 n H L X H CS X H RAS CAS WE X X X X X X Addr X X Invalid Exit Self-refresh (Self-refresh Recovery Idle after tRC) Exit Self-refresh (Self-refresh Recovery Idle after tRC) Illegal Illegal Illegal NOP (Maintain Self-refresh) Invalid Idle after tRC Idle after tRC Illegal Illegal Illegal Illegal Illegal Function Notes
L L L L L Selfrefresh Recovery L H H H H H H H
H H H H L X H H H H H H L
L L L L X X H L L L L X X
H H H L X X X H H H L X X
H H L X X X X H H L X X X
H L X X X X X H L X X X X
X X X X X X X X X X X X X
(Continued)
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MB81F161622B-60/-70/-80
Current State Power Down
CKE CKE n-1 n H L L L L L X H H L H H H H H H H L L L L L L L X
CS X H L X L L H L L L L H L L L L L L X
RAS CAS WE X X H X L H X H L L L X H H H L L L X X X H X X L X X H L L X H H L H L L X X X H X X X X X X H L X H L X X H L X
Addr X X X X X X MODE MODE MODE X MODE X X X X X X X X Invalid
Function
Notes
Exit Power Down Mode Idle Exit Power Down Mode Idle NOP (Maintain Power Down Mode) Illegal Illegal Refer to the Operation Command Table Refer to the Operation Command Table Refer to the Operation Command Table Auto-refresh Refer to the Operation Command Table Power Down Power Down Illegal Illegal Illegal Self-refresh Illegal Invalid
Both Banks Idle
H H H H H H H H H H H H L
(Continued)
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MB81F161622B-60/-70/-80
(Continued)
Current State Bank Active Bank Activating Read/Write CKE CKE n-1 n H H L Clock Suspend H L L Any State Other Than Listed Above H H L H L X X H L H L X CS X X X X X X X X X RAS CAS WE X X X X X X X X X X X X X X X X X X X X X X X X X X X Addr X X X X X X X X X Function Notes
Refer to the Operation Command Table Begin Clock Suspend Next Cycle Invalid Invalid Exit Clock Suspend Next Cycle Maintain Clock Suspend Refer to the Operation Command Table Illegal Invalid
Notes: *1. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle. Illegal means don't used command. If used, power up sequence be asserted after power shut down. *2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that bank. *3. Illegal if any bank is not idle. *4. Must satisfy bus contention, bus turn around, and/or write recovery requirements. *5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP). *6. SELF command should only be issued after the last read data have been appeared on DQ. *7. MRS command should only be issued on condition that all DQ are in Hi-Z.
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MB81F161622B-60/-70/-80
s FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode, and mode register. The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined by commands and all operations are referenced to a positive clock edge. Fig.2 shows the basic timing diagram differences between SDRAMs and DRAMs. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column addresses for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to justify the SDRAM operation and function into desired system conditions. MODE REGISTER TABLE shows how SDRAM can be configured for system requirement by mode register programming.
CLOCK (CLK) AND CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode(standby) is entered with CKE = Low and this will make extremely low standby current.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High , command signals are negated but internal operation such as burst cycle will not be suspended. If such a control isn't needed, CS can be tied to ground level.
COMMAND INPUTS (RAS, CAS AND WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge of the CLK determines SDRAM operation. Refer to FUNCTIONAL TRUTH TABLE in page 5.
ADDRESS INPUTS (A0 to A10)
Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of 19 address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV), 11 Row addresses are initially latched and the remainder of 8 Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (A11)
This SDRAM has two banks and each bank is organized as 512 K words by 16-bit. Bank selection by A11 occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT or WRITA), and precharge command (PRE).
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MB81F161622B-60/-70/-80
DATA INPUTS AND OUTPUTS (DQ0 to DQ15)
Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input: tRAC : from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.) tCAC : from the read command when tRCD is greater than tRCD (min).(This parameter is reference only.) tAC : from the clock edge after tRAC and tCAC. The polarity of the output data is identical to that of the input. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH).
DATA I/O MASK (DQML/DQMU)
DQML and DQMU are active high enable inputs and have an output disable and input mask function. During burst cycle and when DQML/DQMU = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. DQML controls lower byte (DQ0 to DQ7) and DQMU controls upper byte (DQ8 to DQ15).
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1,2,4 or 8 bits of boundary. In order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: Current Stage Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write Next Stage Burst Read Burst Write Burst Write Burst Read Precharge Precharge Method (Assert the following command) Read Command 1st Step 2nd Step Mask Command (Normally 3 clock cycles) Write Command after lOWD
Write Command Read Command Precharge Command Precharge Command
The burst type can be selected either sequential or interleave mode if burst length is 2,4 or 8. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address(=0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column address is even (0), the next address will be odd (1), or vice-versa.
(Continued)
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MB81F161622B-60/-70/-80
(Continued)
When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write operation. The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address(=0). Burst Length 2 Stating Column Address A2 A1 A0 XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111
Sequential Mode 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Interleave 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps round to first column address (=0) and continues to count until interrupted by the news Read (READ) /Write (WRIT) , Precharge (PRE) , or Burst Stop (BST) command. The selection of Auto-precharge option is illegal during the full column burst operation except write command at BURST READ & SINGLE WRITE mode. The BST command is applicable to terminated burst operation. If the BST command is asserted burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When read mode is interrupted by BST command, the output will be in High-Z. For the detail rule, please refer to TIMING DIAGRAM-8. When write mode is interrupted by BST command, the data to be applied at the same time with BST command will be ignored.
BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this mode, burst read operation does not affected by this mode.
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MB81F161622B-60/-70/-80
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs', requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE). With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP). The precharged bank is selected by combination of AP and A11 when Precharge command is asserted. If AP = High, both banks are precharged regardless of A11 (PALL). If AP = Low, a bank to be selected by A11 is precharged (PRE). The Auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command assertion. This Auto-precharge is entered by AP = High when a read or write command is asserted. Refer to FUNCTION TRUTH TABLE.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 15.6 s or a total 4096 refresh commands within a 64 ms period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh function until cancelled by SELFX. The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once SDRAM enters the self-refresh mode, all inputs except for CKE will be "don't care" (either logic high or low level state) and outputs will be in a High-Z state. During a Self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after last read data has been appeared on DQ.
SELF-REFRESH EXIT (SELFX)
To Exit SElf-Refresh mode, apply minimum tCKSP before CKE brought high, and then the NOP command (NOP) or the Deselect command (DESL) should be asserted within minimum tRC. Refer to Timing Diagram for the detail. It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE in page 33. The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of SDRAM. Refer to POWER-UP INITIALIZATION below.
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MB81F161622B-60/-70/-80
POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. 2. 3. 4. 5. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input. Maintain stable power, stable clock, and NOP condition for a minimum of 200 s. Precharge all banks by Precharge (PRE) or Precharge All command (PALL). Assert minimum of 2 Auto-refresh command(REF). Program the mode register by Mode Register Set command(MRS).
In addition, it is recommended DQML/DQMU and CKE to track VCC to insure that output is High-Z state. The Mode Register Set command (MRS) can be set before 2 Auto-refresh command (REF).
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MB81F161622B-60/-70/-80
Fig. 2 - BASIC TIMING FOR CONVENTIONAL DRAM vs. SYNCHRONOUS DYNAMIC RAM
Active CLK CKE H tSI CS tHI H H Read/Write Precharge
RAS
CAS H : Read WE L : Write Address BA (A11) RA DQ Burst Length = 4 Row Address Select RAS Column Address Select Precharge BA (A11) CA BA (A11) AP (A10)
CAS Latency = 2
CAS
DQ
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MB81F161622B-60/-70/-80
Fig. 3 - STATE DIAGRAM (Simplified for Single Bank Operation State Diagram)
MRS MODE REGISTER SET IDLE
SELF SELFX SELF REFRESH
CKE CKE\(PD)
REF
CKE\ BANK ACTIVE SUSPEND CKE BANK ACTIVE
ACTV
POWER DOWN
AUTO REFRESH
WRIT WRIT WRITA WRITE SUSPEND CKE WRITE CKE\ WRITA READA READ WRIT READA PRE or PALL
READ READ
READ
CKE\ CKE
READ SUSPEND
WRITA
READA
WRITE SUSPEND
CKE CKE\
WRITE WITH AUTO PRECHARGE PRE or PALL
READ WITH CKE\ AUTO CKE PRECHARGE PRE or PALL
READ SUSPEND
POWER ON
PRE or PALL
PRECHARGE
POWER APPLIED DEFINITION OF ALLOWS Manual Input Automatic Sequence
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MB81F161622B-60/-70/-80
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION
READA WRITA READ ACTV PALL SELF tRSC
*2 *2
WRT
MRS
PRE
First command
MRS
tRSC
tRSC
*4 *4
tRSC
tRSC
tRSC
ACTV
tRCD
tRCD
tRCD
*1
tRCD
*1
tRAS
tRAS
READ
*2 *2
1
1
1
1
1
1
READA
BL + tRP
BL + tRP tWR tWR 1 1 tDPL tDPL
BL + tRP
REF
Second command (same bank)
BL + tRP
WRIT
WRITA
tDAL
*3
tDAL
*3
tDAL
*3
tDAL
*3
PRE
tRP
*3
tRP
*3
tRP
tRP
tRP
*3
tRP
*3
PALL
tRP
tRP
tRP
tRP
tRP
tRP
REF
tRC
tRC
tRC
tRC
tRC
tRC
SELFX Notes: *1. *2. *3. *4.
tRC
tRC
tRC
tRC
Assume no I/O conflict. If tRP tCK, minimum latency is a sum of BL + CL. Assume Output is in High-Z state. Assume tRAS is satisfied. Illegal Command
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MB81F161622B-60/-70/-80
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 2 BANK OPERATION
Second
READA
WRITA
READ
ACTV
PALL
First command
MRS
tRSC
tRSC
*1 *2 *2 *2 *2
tRSC
*7
tRSC
tRSC
tRSC
ACTV
tRRD
*1
1
*2
1
*2
1
*2 *3
1
*2 *3
1
*7
tRAS
*8
READ
*9 *1 *4
1
*1
1
1
1
1
1
1
*1 *4 *1 *4
READA
BL + tRP
1
*1
1
*2
1
*2
1
*2
1
*2
1
*7 *8
BL + tRP 1
*1
BL + tRP
WRIT
*9 *1 *4
1
*1
1
1
1
1
1
SELF
*1
WRT
MRS
PRE
WRITA
BL + tRP
*1
1
*1
1
*2
1
*2
1
*2
1
*2
1
BL + 1 + tRP
*1
REF
command (opposite bank)
BL + 1 + tRP
*1
PRE
tRP
1
*1
1
1
1
1
1
tRAS
tRP
*1 *6
tRP
*1 *6
PALL
tRP
tRP
1
1
tRP tRC
tRP tRC
REF
tRC
tRC
tRC
tRC
SELFX Notes: *1. *2. *3. *4. *5. *6. *7. *8. *9.
tRC
tRC
tRC
tRC
Assume opposite bank is in idle state. Assume opposite bank is in active state. Assume no I/O conflict. If tRP tCK, minimum latency is a sum of BL + CL. Assume PALL command dose not affect any operation on opposite bank. Assume Output is in High-Z state. Assume tRAS of opposite bank is satisfied. Assume tRAS(ACTV to PALL) is satisfied. If opposite bank should be interrupted, tRAS of own bank is satisfied.. Illegal Command
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MB81F161622B-60/-70/-80
s MODE REGISTER TABLE
MODE REGISTER SET
A11 0 A10 0 A9 Opcode A8 0 A7 0 A6 A5 CL A4 A3 BT A2 A1 BL A0 ADDRESS MODE REGISTER
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0
Burst Length BT = 0 0 1 0 1 0 1 0 1 1 2 4 8 Reserved Reserved Reserved Full Column BT = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
A9 0 1
Op-code Burst Read & Burst Write Burst Read & Single Write
A3 0 1
Burst Type Sequential (Wrap round, Binary-up) Interleave (Wrap round, Binary-up)
Notes: 1.
When A9 = 1, burst length at Write is always one regardless of BL value.
2. BL = 1 and Full Column are not applicable to the interleave mode.
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MB81F161622B-60/-70/-80
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage of VCC Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Storage Temperature Symbol VCC VIN, VOUT IOUT PD TSTG Value -0.5 to +4.6 -0.5 to +4.6 -50 to +50 1.3 -55 to +125 Unit V V mA W C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature Notes -60 -70/-80 *1 *2 Symbol VCC, VCCQ VCC, VCCQ VSS, VSSQ VIH VIL TA Min. 3.15 3.0 0 2.0 -0.5 0 Typ. 3.3 3.3 0 -- -- -- Max. 3.6 3.6 0 VCC + 0.5 0.8 70 Unit V V V V V C
Notes: *1. Overshoot limit: VIH (max) = VCC +1.5 V with a pulsewidth 5 ns. *2. Undershoot limit: VIL (min) = -1.5 V with a pulsewidth 5 ns WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within theie recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
s CAPACITANCE
(TA = 25C, f = 1 MHz) Parameter Input Capacitance, Except for CLK Input Capacitance for CLK I/O Capacitance Symbol CIN1 CIN2 CI/O Min. 2.5 2.5 4.0 Typ. -- -- -- Max. 5 4 6.5 Unit pF pF pF
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MB81F161622B-60/-70/-80
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 1, 2
Parameter Output High Voltage Output Low Voltage Input Leakage Current (Any Input) Output Leakage Current MB81F161622B-60 MB81F161622B-70 MB81F161622B-80 Reference Spec (100MHz @CL=3) MB81F161622B-60 MB81F161622B-70 MB81F161622B-80 Reference Spec (100MHz @CL=3) ICC1D ICC1S Symbol VOH(DC) VOL(DC) ILI ILO Conditions IOH = -2 mA IOL = 2 mA 0 V VIN VCC; All other pins not under test = 0 V 0 V VIN VCC; Data out disabled Burst: Length = 4, tRC = min for BL = 4, tCK = min, One bank active, Outputs open, Addresses changed up to 3-times during tRC(min), 0 V VIN VCC Burst Length = 4 (each bank), tRC = min for BL = 4(each bank), tCK = min, All banks active, Output open, Addresses changed up to 3-times during tRC(min), 0 V VIN VCC CKE = VIL, All banks idle, tCK = min, Power down mode, 0 V VIN VCC CKE = VIL , All banks idle, CLK = H or L , Power down mode, 0 V VIN VCC CKE = VIH, All banks idle, tCK = min, NOP commands only, Input signals(except to CMD) are changed one times during 3 clock cycles, 0 V VIN VCC CKE = VIH , All banks idle, CLK = H or L, Input signals are stable, 0 V VIN VCC Value Min. 2.4 -- -5 -5 Max. -- 0.4 5 5 150 130 -- 110 90 200 180 -- 160 140 mA mA Unit V V A A
Operating Current (Average Power Supply Current)
ICC2P
--
400 A 400
ICC2PS
Precharge Standby Current (Power Supply Current)
MB81F161622B-60 MB81F161622B-70 MB81F161622B-80 Reference Spec (100MHz @CL=3) ICC2N
-- -- -- --
25 25 25 20
mA
ICC2NS
--
15
(Continued)
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MB81F161622B-60/-70/-80
(Continued)
Parameter Symbol Conditions CKE = VIL, Any bank active, tCK = min, 0 V VIN VCC CKE = VIL, Any bank active, CLK = H or L, 0 V VIN VCC CKE = VIH, Any bank active, tCK = min, NOP commands only, Input signals(except to CMD) are changed one times during 3 clock cycles, 0 V VIN VCC CKE = VIH, Any bank active, CLK = H or L, 0 V VIN VCC tCK = min, Burst Length = 4, Outputs open, Multiple-banks active, Gapless data, 0 V VIN VCC Auto-refresh; tCK = min, tRC = min, 0 V VIN VCC Self-refresh; tCK = min, CKE 0.2 V, 0 V VIN VCC Value Min. -- Max. 5 Unit
ICC3P Active Standby Current (Power Supply Current) ICC3PS MB81F161622B-60 MB81F161622B-70 MB81F161622B-80 Active Standby Current (Power Supply Current) Reference Spec (100MHz @CL=3) ICC3N
mA
-- -- -- --
3 75 65 55
mA mA mA mA
--
50
mA
ICC3NS MB81F161622B-60 Burst mode Current (Average Power Supply Current) MB81F161622B-70 MB81F161622B-80 Reference Spec (100MHz @CL=3) MB81F161622B-60 Refresh Current #1 (Average Power Supply Current) MB81F161622B-70 MB81F161622B-80 Reference Spec (100MHz @CL=3) ICC6 ICC5 ICC4
--
25 150 130
mA
--
110 95 90 80
mA
--
70 60
mA
Refresh Current #2 (Average Power Supply Current)
--
400
A
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MB81F161622B-60/-70/-80
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 2, 3, 4
Parameter Notes Sym bol tCK2 tCK3 tCH tCL tSI tHI tAC2 tAC3 tLZ tHZ2 tHZ3 tOH tREFI tT
MB81F161622B MB81F161622B MB81F161622B Reference Spec -60 -70 -80 (100MHz@CL=3) Unit
Min. -- 6.0 2.5 2.5 2 1 -- -- 0 -- 2 -- 2 -- 0.5 3
Max. -- -- -- -- -- -- -- 5.5 -- -- 6 -- -- 15.6 2 --
Min. 10.5 7.0 2.5 2.5 2 1 -- -- 0 3 2 2 2 -- 0.5 3
Max. -- -- -- -- -- -- 7 6 -- 7 6 -- -- 15.6 2 --
Min. 12 8 3 3 2.5 1 -- -- 0 3 3 2 2 -- 0.5 3
Max. -- -- -- -- -- -- 7 6 -- 6 6 -- -- 15.6 2 --
Min. 15 10 3 3 2.5 1 -- -- 0 3 3 2 2 -- 0.5 3
Max. -- -- -- -- -- -- 7 6 -- 7 6 -- -- 15.6 2 -- ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns
Clock Period
CAS Latency = 2 CAS Latency = 3
Clock High Time Clock Low Time Input Setup Time Input Hold Time Access Time from Clock (tCK = min) *5,6 CAS Latency = 2 CAS Latency = 3
Output in Low-Z Output in High-Z CAS Latency = 2 *7 CAS Latency = 3 CAS Latency = 2 CAS Latency = 3
Output Hold Time
Time between Auto-refresh command Interval Transition Time
CKE Setup time for Power Down tCKSP Exit
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MB81F161622B-60/-70/-80
BASE VALUES FOR CLOCK COUNT/LATENCY
Parameter RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time Data-in to Precharge Lead Time Data-in to Active/Refresh Command Period *9 Symbol *8 tRC tRP tRAS tRCD tWR tDPL
MB81F161622B -60 MB81F161622B -70 MB81F161622B Reference Spec -80 (100MHz@CL=3) Unit
Notes
Min. 54.0 18.0 36 18.0 6.0 6.0 --
2cyc+tRP
Max. -- -- 100000 -- -- -- -- -- -- --
Min. 63.0 21.0 42 21.0 7.0 7.0
1cyc+tRP 2cyc+tRP
Max. -- -- 100000 -- -- -- -- -- -- --
Min. 72 24 48 24 8 8
1cyc+tRP 2cyc+tRP
Max. -- -- 100000 -- -- -- -- -- -- --
Min. 80 30 50 30 10 10
1cyc+tRP 2cyc+tRP
Max. -- -- ns ns
100000 ns -- -- -- -- -- -- -- ns ns ns ns ns ns ns
CAS tDAL2 Latency = 2 CAS tDAL3 Latency = 3 tRSC tRRD
Mode Register Set Cycle Time RAS to RAS Bank Active Delay Time
12 12
14 14
16 16
20 20
CLOCK COUNT FORMULA Note10
Clock Base Value Clock Period (Round off a whole number)
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MB81F161622B-60/-70/-80
LATENCY-FIXED VALUES (The latency values on these parameters are fixed regardless of clock period.)
Parameter
Reference Spec Notes Sym- MB81F161622B MB81F161622B MB81F161622B (100MHz@CL=3) Unit bol -60 -70 -80
CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay
lCKE lDQZ lDQD lOWD lDWD
1 2 0 2 0 -- 3 -- 3 1 1
1 2 0 2 0 2 3 2 3 1 1
1 2 0 2 0 2 3 2 3 1 1
1 2 0 2 0 2 3 2 3 1 1
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
CL = 2 lROH2 CL = 3 lROH3 CL = 2 lBSH2 CL = 3 lBSH3 lCCD lCBD
CAS to CAS Delay (min) CAS Bank Delay (min)
Notes: *1. ICC depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; the specified values are obtained with the output open and no termination register. *2. An initial pause (DESL or NOP) of 200 s is required after power-up followed by a minimum of 2 Auto-refresh cycles. *3. AC characteristics assume tT = 1 ns and 30 pF of capacitive load. *4. 1.4 V is the reference level for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max). *5. Assumes tRCD is satisfied. *6. tAC also specifies the access time at burst mode. *7. Specified where output buffer is no longer driven. *8. Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP). *9. Operation within the tRCD (min) ensures that access time is determined by tRCD(min) + tAC(max); if tRCD is greater than the specified tRCD (min), access time is determined by tAC. *10. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number).
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MB81F161622B-60/-70/-80
Fig. 4 - EXAMPLE OF AC TEST LOAD CIRCUIT
R1 = 50 Output 1.4 V
CL = 30 pF
LVTTL
Note: AC characteristics are measured in this condition. This load circuits are not applicable for VOH and VOL.
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MB81F161622B-60/-70/-80
Fig. 5 - TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME
tCK tCH 2.4 V CLK 1.4 V 0.4 V tSI Input (Control, Addr. & Data) tAC tLZ tOH tHI 2.4 V 1.4 V 0.4 V tHZ tCL
2.4 V Output 0.4 V 1.4 V
Note: Reference level of input signal is 1.4 V for LVTTL. Access time is measured at 1.4 V for LVTTL.
Fig. 6 - TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT
CLK
Don't Care tCKSP (min) 1 clock (min)
CKE
Command
Don't Care
NOP
NOP
ACTV
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MB81F161622B-60/-70/-80
Fig. 7 - TIMING DIAGRAM, PULSE WIDTH
CLK
Input (Control)
, tRC, tRP tRAS, tRCD, tWR, tREF, tDPL, tDAL, tRSC, tRRD, tCKSP
Command Command
Note: These parameter are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the latency value from the rising edge of CKE. Measurement reference voltage is 1.4 V.
Fig. 8 - TIMING DIAGRAM, ACCESS TIME
CLK
tRAC
RAS
tRCD
tCAC
CAS
(CAS Latency - 1) x tCK
tAC
DQ (Output)
Q(Valid)
Note: tRAC, tCAC are a reference value. Data can be obtained after both tCAC = (CL - 1) x tCK and tAC are satisfied.
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE ICKE (1 clock) CLK (Internal) *1 *2 ICKE (1 clock) *1 *2
DQ (Read)
Q1
Q2
(No Change)
*2
Q3
(No Change)
*2
Q4
DQ (Write)
D1
*3 Not Written
D2
*3 Not Written
D3
D4
Notes: *1. The latency of CKE (lCKE) is one clock. *2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output remain the same data. *3. During the write mode, data at the next clock of CSUS command is ignored.
TIMING DIAGRAM - 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
CLK tCKSP CKE 1 clock (min)
Command
NOP
*1
*2 PD(NOP)
Don't Care tREF (max)
*3 NOP
*3 NOP
ACTV
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2. Precharge command can be posted in conjunction with CKE when burst mode is ended at this clock. *3. The ACTV command can be latched after tCKSP (min) + 1clock (min). It is should be asserted NOP command in conjunction with CKE.
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS tRCD (min) CAS ICCD (1 clock) ICCD ICCD ICCD
Address
Row Address
Column Address
Column Address
Column Address
Column Address
Column Address
Note: CAS to CAS address delay can be one or more clock period.
TIMING DIAGRAM - 4 : DIFFERENT BANK ADDRESS INPUT DELAY
CLK tRRD (min)
RAS tRCD (min) CAS tRCD (min) Address Row Address Row Address Column Address Column Address Column Address Column Address ICBD ICBD
A11(BA)
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 5 : DQM-INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQML-DQMU (@ Read) IDQZ (2 clocks) DQ (@ Read)
Q1
Q2
Hi-Z
Q4
End of burst
DQML-DQMU (@ Write) IDQD (same clock) DQ (@ Write) D1 Masked D3 D4
End of burst
TIMING DIAGRAM - 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK tRAS (min) Command ACTV Precharge
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 7 : READ INTERRUPTED BY PRECHARGE (Example @ CL = 2, BL = 4)
CLK
Command
Precharge IROH (2 clocks)
DQ
Q1
Hi-Z
Command
Precharge IROH (2 clocks)
DQ
Q1
Q2
Hi-Z
Command
Precharge IROH (2 clocks)
DQ
Q1
Q2
Q3
Hi-Z
Command
Precharge No effect (end of burst)
DQ
Q1
Q2
Q3
Q4
Note: In case of CL = 2, the lROH is 2 clock. In case of CL = 3, the lROH is 3 clock.
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 8 : READ INTERRUPTED BY BURST STOP (Example @ BL = Full Column)
CLK
Command (CL = 2)
BST IBSH (2 clocks)
DQ
Qn - 2
Qn - 1
Qn
Qn + 1
Hi-Z
Command (CL = 3)
BST IBSH (3 clocks)
DQ
Qn - 2
Qn - 1
Qn
Qn + 1
Qn + 2
Hi-Z
Note: The selection of Auto-precharge option is illegal during the full column burst operation except Write command at BURST READ & SINGLE WRITE mode.
TIMING DIAGRAM - 9 : WRITE INTERRUPT BY BURST STOP (Example @ CL = 2)
CLK
Command
BST
Command
DQ
Last Data-In
Masked by BST
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 10 : WRITE INTERUPTED BY PRECHARGE (Example @ CL = 3)
CLK
Command
Precharge tDPL(min) tRP(min)
Active
DQ
Data-In
Last Data-In
Masked by PRE
Note: The precharge command (PRE) should only be issued after the tDPL of final data input, is satisfied.
TIMING DIAGRAM - 11 : READ INTERRUPTED BY WRITE (Example @ CL = 3, BL = 4)
CLK IOWD (2 clocks) Command Read Write
DQM
(DQML/DQMU)
Note 1
Note 2 IDQZ (2 clocks)
Note 3 IDWD (same clock) Data In Masked Data In
DQ
Data Out
Notes: 1. First DQM makes high-impedance state High-Z between last output and first input data. 2. Second DQM makes internal output data mask to avoid bus contention. 3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention.
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 12 : WRITE TO READ TIMING (Example @ CL = 3, BL = 4)
CLK tWR (min) Command Write Read
DQM
(DQML/DQMU)
(CL-1) x tCK DQ D1 D2 D3 Masked by Read
tAC (max)
Q1
Q2
Note: Read command should be issued after tWR of final data input is satisfied if read command is applied to the same bank.
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 13 : READ WITH AUTO-PRECHARGE (Example @ CL = 2, BL = 2 Applied to same bank)
CLK tRAS (min) tRP (min)
Command
ACTV
READA 2 clocks *1 (same Value as BL)
NOP or DESL
ACTV
BL + tRP(min) *2
DQM
(DQML/DQMU)
DQ
Q1
Q2
Notes: *1. Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as Burst Length (BL) after READA command is asserted. *2. Next ACTV command should be issued after BL + tRP(min) from READA command.
TIMING DIAGRAM - 14 : WRITE WITH AUTO-PRECHARGE (Example @ CL = 2, BL = 2 Applied to same bank)
tRAS (min) CLK
1 tDPL (min)
tDAL (min) BL + tRP (min) *5
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM
(DQML/DQMU)
DQ
D1
D2
Notes: *1. Precharge at write with Auto-precharge is started after the tDPL from the end of burst. *2.Even if the final data is masked by DQM, the precharge does not start the clock of final data input. *3.Once auto precharge command is asserted, no new command within the same bank can be issued. *4.Auto-precharge command doesn't affect at full column burst operation except Burst Read & Single Write mode. *5.Next command should be issued after BL + tRP(min) at CL = 2, BL + 1+ tRP(min) at CL = 3 from WRITEA command.
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 15 : AUTO-REFRESH TIMING
CLK
Command
REF*1
NOP *3
NOP *4 tRC (min)
NOP
REF
NOP tRC (min)
*4 Command
A11 (BA)
Don't Care
Don't Care
Don't Care
BA
Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF). *2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter. *3. Either NOP or DESL command should be asserted during tRRD and tRC period while Auto-refresh mode. *4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the last REF command.
TIMING DIAGRAM - 16 : SELF-REFRESH ENTRY AND EXIT TIMING
CLK tCKSP (min) tRC(min) *4
CKE
Command
NOP*1
SELF
Don't Care
NOP *2
SELFX
NOP *3 Command
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF). *2. The Self-refresh Exit command (SELFX) is latched after tCKSP (min). It is recommended to apply NOP command in conjunction with CKE. It is also recommended to apply minimum of 4 clocks to stabilize external clock prior to SELFX command. *3. Either NOP or DESL command can be used during tRC period. *4. CKE should be held High within tRC(min) period after tCKSP
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MB81F161622B-60/-70/-80
TIMING DIAGRAM - 17 : MODE REGISTER SET TIMING
CLK
tRSC
Command
MRS
NOP or DESL
ACTV
Address
Mode
ROW Address
Note: The Mode Register Set command (MRS) should be only asserted after all banks have been precharged.
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MB81F161622B-60/-70/-80
s PACKAGE DIMENSION
50-pin plastic TSOP (II) (FPT-50P-M05) Resin protrusion. (Each side: 0.15 (.006) Max)
50
26
Details of "A" part
0.15(.006)
0.25(.010) "A" INDEX LEAD No.
1 25
0.10(.004) MAX 0.40(.016) MAX
* 20.950.10
(.825.004) 0.300.10 (.012.004) 0.13(.005)
M
1.150.05 (.045.002)
11.760.20 (.463.008) 10.160.10 (.400.004)
0.1250.05 (.005.002)
0.80(.031) TYP.
0.10(.004) 19.20(.756) REF.
0.500.10 (.020.004) 0.05(.002)MIN (STAND OFF)
10.760.20 (.424.008)
C
1995 FUJITSU LIMITED F50005S-2C-1
44
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MB81F161622B-60/-70/-80
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inhereut chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9901 (c) FUJITSU LIMITED Printed in Japan
45

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